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ADE7854/ADE7858/ADE7868/ADE7878
I 2 C Read Operation
The read operation using the I 2 C interface of the ADE7854 /
ADE7858 / ADE7868 / ADE7878 is accomplished in two stages.
The first stage sets the pointer to the address of the register. The
second stage reads the content of the register.
As seen in Figure 87, the first stage initiates when the master
generates a start condition and consists in one byte representing
the address of the ADE7854 / ADE7858 / ADE7868 / ADE7878
followed by the 16-bit address of the target register. The ADE78xx
acknowledges every byte received. The address byte is similar to
the address byte of a write operation and is equal to 0x70 (see
the I2C Write Operation section for details). After the last byte
of the register address has been sent and acknowledged by the
Data Sheet
ADE7854 / ADE7858 / ADE7868 / ADE7878 , the second stage
begins with the master generating a new start condition followed
by an address byte. The most significant seven bits of this address
byte constitute the address of the ADE78xx , and they are equal to
0111000b. Bit 0 of the address byte is a read/write bit. Because this
is a read operation, it must be set to 1; thus, the first byte of the
read operation is 0x71. After this byte is received, the ADE78xx
generates an acknowledge. Then, the ADE78xx sends the value
of the register, and after every eight bits are received, the master
generates an acknowledge. All the bytes are sent with the most
significant bit first. Because registers can have 8, 16, or 32 bits,
after the last bit of the register is received, the master does not
acknowledge the transfer but generates a stop condition.
15
8
7
0
S 0 1 1 1 0 0 0 0
SLAVE ADDRESS
A MSB 8 BITS OF
C REGISTER ADDRESS
K
A LSB 8 BITS OF
C REGISTER ADDRESS
K
A
C
K
ACKNOWLEDGE
GENERATED BY
ADE78xx
ACKNOWLEDGE
GENERATED BY
MASTER
N
O
31
A
24 C 23
K
A
16 C 15
K
A
8 C
K
7
A
C
0 K
S
0
1
1
1
0
0
0 1
S
SLAVE ADDRESS
A
C
K
BYTE 3 (MSB)
OF REGISTER
BYTE 2 OF
REGISTER
BYTE 1 OF
REGISTER
BYTE 0 (LSB)
OF REGISTER
ACKNOWLEDGE
GENERATED BY
ADE78xx
Figure 87. I 2 C Read Operation of a 32-Bit Register
Rev. H | Page 70 of 100
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